Base classes


class systemrdl.component.Component

Base class for all component types

Inheritance diagram of systemrdl.component
children: List[Component]

List of Component instances that are direct descendants of this component.

Child components are sorted as follows:

  • Signals first

  • All other components follow.

  • AddressableComponents are sorted by ascending base_addr

  • Fields are sorted by ascending low bit

def_src_ref: SourceRefBase | None

Source Reference for the component definition

external: bool

True if instance type is external. False if internal.

get_scope_path(scope_separator: str = '::') str | None

Generate a string that represents this component’s declaration namespace scope.

Returns None if scope is not known or not applicable.

For example, the following SystemRDL snippet:

reg my_reg_t {
    field {} x;

addrmap top {
    my_reg_t foo;
    reg my_other_reg_t {
        field {} y;
    } bar;
    reg {
        field {} z;
    } baz, xyz;

… results in:

  • Field x of hierarchical path was declared in the lexical scope my_reg_t

  • Field y of hierarchical path was declared in the lexical scope top::my_other_reg_t

  • Both fields z of hierarchical paths top.baz.z and were declared in the same lexical scope top::baz

  • Register foo was declared in the root scope which is represented by an empty string.


scope_separator (str) – Override the separator between namespace scopes

inst_name: str | None

Name of instantiated element

inst_src_ref: SourceRefBase | None

Source Reference for the component instantiation.

is_instance: bool

If instantiated, set to True

original_def: Component | None

Reference to original Component definition this instance is derived from.

Importers may leave this as None if appropriate.

parent_scope: Component

Reference to parent Component definition that lexically encloses this component type definition.

May remain None if scope is not known or not applicable.


This represents the parent lexical scope! This does not refer to the hierarchical parent of this component.

property_src_ref: Dict[str, SourceRefBase]

Source Reference for each explicit property assignment (if available)

type_name: str | None

Named definition identifier. If declaration was anonymous, instantiation type names inherit the first instance’s name. The type name of parameterized components is normalized based on the instance’s parameter values.

If this is a non-instantiated component (referenced via an instance’s original_def), then it will contain either the original type name, or None if the declaration was anonymous.

Importers may leave this as None if an appropriate type name cannot be imported.


class systemrdl.component.AddressableComponent

Base class for all components that can have an address

addr_align: int | None

Address alignment if explicitly assigned by user.

addr_offset: int

Address offset from the parent component. If left as None, compiler will resolve with inferred value.

array_dimensions: List[int] | None

List of sizes for each array dimension. Last item in the list iterates the most frequently.

array_stride: int | None

Address offset between array elements. If left as None, compiler will resolve with inferred value.

is_array: bool

If true, then array_dimensions and array_stride are valid.

property n_elements: int

Total number of array elements. If array is multidimensional, array is flattened. Returns 1 if not an array.


class systemrdl.component.VectorComponent

Base class for all components that are vector-like

high: int

High index of bit range

low: int

Low index of bit range

lsb: int

Bit position of least significant bit

msb: int

Bit position of most significant bit

width: int

Width of vector in bits

Component Types


class systemrdl.component.Signal


class systemrdl.component.Field


class systemrdl.component.Reg
alias_primary_inst: Reg | None

Reference to primary register Component instance

is_alias: bool

If true, then alias_primary_inst is valid

is_msb0_order: bool

If true, fields are to be arranged in msb0 order

New in version 1.7.


class systemrdl.component.Regfile


class systemrdl.component.Addrmap


class systemrdl.component.Mem