SystemRDL Property Reference
This page summarizes all of the properties described in the SystemRDL spec. This is only intended for quick reference. For more details on usage and semantics, refer to the full SystemRDL 2.0 specification.
Global Properties
Name |
Type |
Description |
---|---|---|
desc |
string |
Describes the component’s purpose. |
ispresent |
boolean |
Used to configure the activation of component instances. Setting |
name |
string |
Specifies a more descriptive name |
Field Properties
Name |
Type |
Description |
---|---|---|
onread |
onreadtype |
Read side-effect. |
onwrite |
onwritetype |
Write side-effect. |
rclr |
boolean |
Clear on read |
rset |
boolean |
Set on read |
singlepulse |
boolean |
The field asserts for one cycle when written 1 and then clears back to 0 on the next cycle. This creates a single-cycle pulse on the hardware interface. |
sw |
accesstype |
Programmer’s ability to read/write a field. |
swacc |
boolean |
Indicates an output signal shall be generated. Assert when field is software accessed. |
swmod |
boolean |
Indicates an output signal shall be generated. Assert when field is modified by software (written or read with a set or clear side effect). |
swwe |
boolean, bit, instance reference |
Software write-enable. active high. |
swwel |
boolean, bit, instance reference |
Software write-enable. active low. |
woclr |
boolean |
Write one to clear |
woset |
boolean |
Write one to set |
Name |
Type |
Description |
---|---|---|
anded |
boolean |
Indicates an output signal shall be generated. Logical AND of all bits in field. |
fieldwidth |
longint unsigned |
Determines the width of all instances of the field |
hw |
accesstype |
Design’s ability to sample/update a field. |
hwclr |
boolean, instance reference |
Hardware clear. |
hwenable |
instance reference |
Determines which bits may be updated after any write enables, hard- ware clears/sets or counter increment has been performed. Bits that are set to 1 will be updated. |
hwmask |
instance reference |
Determines which bits may be updated after any write enables, hard- ware clears/sets or counter increment has been performed. Bits that are set to 1 will not be updated. |
hwset |
boolean, instance reference |
Hardware set. |
ored |
boolean |
Indicates an output signal shall be generated. Logical OR of all bits in field. |
we |
boolean, instance reference |
Write-enable (active high). |
wel |
boolean, instance reference |
Write-enable (active low). |
xored |
boolean |
Indicates an output signal shall be generated. Logical XOR of all bits in field. |
Name |
Type |
Description |
---|---|---|
counter |
boolean |
Field implemented as a counter. |
decr |
instance reference |
References the counter’s decrement signal. Use to actually decrement the counter, i.e, the actual counter decrement is controlled by another component or signal (active high). |
decrsaturate |
boolean, bit, instance reference |
Indicates the counter saturates in the decrementing direction. |
decrvalue |
bit, instance reference |
Decrement counter by specified value. |
decrwidth |
longint unsigned |
Width of the interface to hardware to control decrementing the counter externally. |
incr |
instance reference |
References the counter’s increment signal. Use to actually increment the counter, i.e, the actual counter increment is controlled by another component or signal (active high). |
incrsaturate |
boolean, bit, instance reference |
Indicates the counter saturates in the incrementing direction. |
incrthreshold |
boolean, bit, instance reference |
Indicates the counter has a threshold in the incrementing direction. |
incrvalue |
bit, instance reference |
Increment counter by specified value. |
incrwidth |
longint unsigned |
Width of the interface to hardware to control incrementing the counter externally. |
overflow |
boolean |
Indicates an output signal shall be generated. Asserted when counter overflows or wraps. |
saturate |
boolean, bit, instance reference |
This is an alias of |
threshold |
boolean, bit, instance reference |
This is an alias of |
underflow |
boolean |
Indicates an output signal shall be generated. Asserted when counter underflows or wraps. |
Name |
Type |
Description |
---|---|---|
enable |
instance reference |
Defines an interrupt enable (the inverse of |
haltenable |
instance reference |
Defines a halt enable (the inverse of |
haltmask |
instance reference |
Defines a halt mask (the inverse of |
intr |
boolean |
Interrupt, part of interrupt logic for a register. |
mask |
instance reference |
Defines an interrupt mask (the inverse of |
sticky |
boolean |
Defines the entire field as sticky; i.e., the value of the associated interrupt field shall be locked until cleared by software (write or clear on read). |
stickybit |
boolean |
Defines each bit in a field as sticky (the default); i.e., the value of each bit in the associated interrupt field shall be locked until the individual bits are cleared by software (write or clear on read). |
Name |
Type |
Description |
---|---|---|
dontcompare |
boolean, bit |
Indicates the components read data shall be discarded and not compared against expected results. |
donttest |
boolean, bit |
Indicates the component should not be included in structural testing. |
hdl_path_gate_slice |
string[] |
Assigns a list of gate-level hdl_path. |
hdl_path_slice |
string[] |
Assigns a list of RTL hdl_path. |
Name |
Type |
Description |
---|---|---|
encode |
enum type reference |
Binds an enumeration to a field. |
next |
instance reference |
The next value of the field |
paritycheck |
boolean |
Indicates whether this field is to be checked by parity. |
precedence |
precedencetype |
Controls whether precedence is granted to hardware (hw) or software (sw) when contention occurs. |
reset |
bit, instance reference |
The reset value for the field when resetsignal is asserted. |
resetsignal |
instance reference |
Reference to the signal used to reset the field |
Register Properties
Name |
Type |
Description |
---|---|---|
accesswidth |
longint unsigned |
Specifies the minimum software access width operation that may be performed on the register. |
dontcompare |
boolean |
Indicates the components read data shall be discarded and not compared against expected results. |
donttest |
boolean |
Indicates the component should not be included in structural testing. |
errextbus |
boolean |
The associated register, external regfile, or external addrmap has error input. |
hdl_path |
string |
Assigns the RTL hdl_path. |
hdl_path_gate |
string |
Assigns the gate-level hdl_path. |
regwidth |
longint unsigned |
Specifies the bit-width of the register |
shared |
boolean |
Defines a register as being shared in different address maps. |
Address Map Properties
Name |
Type |
Description |
---|---|---|
addressing |
addressingtype |
Specifies how component addresses are to be inferred if not explicitly defined. |
alignment |
longint unsigned |
Specifies alignment of all instantiated components in the associated register file or address map. |
bigendian |
boolean |
Uses big-endian architecture in the address map. |
bridge |
boolean |
Defines the parent address map as being a bridge. This shall only be applied to the root address map which contains the different views of the sub address maps. |
dontcompare |
boolean |
Indicates the components read data shall be discarded and not compared against expected results. |
donttest |
boolean |
Indicates the component should not be included in structural testing. |
errextbus |
boolean |
The associated register, external regfile, or external addrmap has error input. |
hdl_path |
string |
Assigns the RTL hdl_path. |
hdl_path_gate |
string |
Assigns the gate-level hdl_path. |
littleendian |
boolean |
Uses little-endian architecture in the address map. |
lsb0 |
boolean |
Specifies register bit-fields in an address map are defined as |
msb0 |
boolean |
Specifies register bit-fields in an address map are defined as |
rsvdset |
boolean |
The read value of all fields not explicitly defined is set to 1 if |
rsvdsetX |
boolean |
The read value of all fields not explicitly defined is unknown if |
sharedextbus |
boolean |
Forces all external registers to share a common bus. |
Register File Properties
Name |
Type |
Description |
---|---|---|
alignment |
longint unsigned |
Specifies alignment of all instantiated components in the associated register file or address map. |
dontcompare |
boolean |
Indicates the components read data shall be discarded and not compared against expected results. |
donttest |
boolean |
Indicates the component should not be included in structural testing. |
errextbus |
boolean |
The associated register, external regfile, or external addrmap has error input. |
hdl_path |
string |
Assigns the RTL hdl_path. |
hdl_path_gate |
string |
Assigns the gate-level hdl_path. |
sharedextbus |
boolean |
Forces all external registers to share a common bus. |
Memory Properties
Name |
Type |
Description |
---|---|---|
hdl_path_gate_slice |
string[] |
Assigns a list of gate-level hdl_path. |
hdl_path_slice |
string[] |
Assigns a list of RTL hdl_path. |
mementries |
longint unsigned |
The number of memory entries. |
memwidth |
longint unsigned |
The memory entry bit width. |
sw |
accesstype |
Programmer’s ability to read/write a field. |
Signal Properties
Name |
Type |
Description |
---|---|---|
activehigh |
boolean |
Signal is active high (state of 1 means ON). |
activelow |
boolean |
Signal is active low (state of 0 means ON). |
async |
boolean |
Signal is asynchronous to the clock of the component. |
cpuif_reset |
boolean |
Default signal to use for resetting the software interface logic. If |
field_reset |
boolean |
Default signal to use for resetting field implementations. If |
signalwidth |
longint unsigned |
Width of the signal. |
sync |
boolean |
Signal is synchronous to the clock of the component. |